The Silicon Bottleneck: What Chiplet Architecture Means for the Next Generation of AI Infrastructure
About this session
Every AI system you build eventually hits a hardware ceiling, whether it's training cost, inference latency, or GPU availability. This session pulls back the curtain on chiplet-based design, the industry's answer to monolithic chip scaling limits, and why it directly shapes the compute available to AI builders today. Drawing on public examples like Intel's Data Center GPU Max Series (100B+ transistors across 47 tiles) and NVIDIA's Blackwell (208B transistors, 10 TB/s die-to-die interconnect), we'll unpack how advanced packaging (CoWoS, SoIC, Foveros) and standards like UCIe are redefining what's possible in AI accelerator design, and where the real bottlenecks in cost, bandwidth, and scaling actually live. (612 chars)
Speaker
Key takeaways
- How chiplet architecture and advanced packaging (CoWoS, SoIC, Foveros) are solving the scaling limits of monolithic AI chip design
- Why die-to-die interconnect standards like UCIe directly impact the bandwidth, cost, and performance ceilings of the GPUs powering modern AI infrastructure
- A grounded, engineer's view of where AI accelerator hardware is headed next, and what that means for infrastructure and cost planning